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As past decades have witnessed the rapid development of global informatization, hardware technology is presenting increasing indispensability to truly achieve technological innovation, where microelectronics serves as the foundation for the whole industry. Among microelectronic devices and circuits, MOSFET (metal-oxide–semiconductor field-effect transistor) is the fundamental device unit and is fabricated by forming a controlled oxide layer on top of the silicon substrate, such that the gate electrode can be electrically insulated from the channel where current can flow.
In this project, we fabricated, characterized, and tested a 0.45μm gate length NMOS, with a major change in the design to move away from wet-etched thick field oxide for isolation to LOCOS isolation (LOCal Oxidation of Silicon). Although LOCOS adds more steps early in the process flow, it provides more traditional isolation without using complex shallow trench isolation (STI).
Device structure
The fabrication is performed at the Stanford Nanofabrication Facility (SNF) and involves steps of masking, photolithography, dry etching, ion implant, wet oxidation, low pressure chemical CVD, annealing, etc.
Photo credits (also design of process): Krishna Saraswat and his amazing teaching team
Analytical and numerical calculations
The fabrication outcome is analytically calculated (by hand) and numerical simulated (with SENTAURUS software). The below figure illustrates the simulated diffusion profile of the gate structure.
Wafer yield
Test bench
Example result: contact chain test structure
This structure is used to test the metal contact integrity. We expect current flow with applied voltage and the slope is contact resistance multiplied by the number of contacts.
Example result: contact resistance structure
The contact resistance can also be determined via a 6-point Kelvin test structure. We can further draw correlation between the contact resistance and the contact area.
Example test result: threshold voltage of NMOS device
As the switching device, MOSFET is inevitably characterized by its threshold voltage for the consideration of energy consumption. In theory, for the normal MOSFET device, the drain current is proportional to the square of the overdriven voltage. With a given voltage supply, lowering the threshold voltage will increase the VOV and significantly reduce the energy cost during the switched-on period. It is also a complex parameter that relates with other parameters, like doping concentration and Cox, so the threshold voltage can be very sensitive to the fabrication process.
The below figure plots Id and Vgs on a linear scale and separates the NMOS operation into a cutoff (blue), a saturation (yellow), and a triode (green) region.
In the cutoff region, we barely see changes in the drain current, which indicates a higher threshold voltage than expected.
The below figure plots Id and Vgs on a logarithmic scale. The threshold voltage (0.9 V) is determined at the inflection point (knee), where the polarity of the curvature changes.
This is a team project for my graduate course Integrated Circuit Fabrication Laboratory (EE 312) at Stanford University. The team consists of me, Chenkai Mao, Xinyi Wen, and Mingcheng Shi.
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